INDEX PRELIMINARY
MX98725
APPLICATION NOTE
1. INTRODUCTION
The purpose of this application note is to describe the implementation of a PCI bus master 100 Base-TX Fast Ethernet node using MXIC' highly integrated single chip Fast Ethernet NIC controller MX98725. In details, this document presents product overview, programming guide, hardware design and layout recommendations that can help you to quickly and smoothly implement a Fast Ethernet adapter card. As you can find in the MX98725 driver diskette, MXIC already provided a complete set of high quality drivers for easier and more efficient way to interface with MX98725 on the most popular Network Operating Systems. Nevertheless, there are still some special applications or environment not covered in the MX98725 driver diskette. Driver developers, however, could still refer to the section of driver programming guide to accomplish the required driver. It is recommended that you are familiar with the MX98725 data sheet before reading this guide.
2. PRODUCT OVERVIEW
The MX98725 implements the 10/100Mbps MAC layer and Physical layer on a single chip in accordance with the IEEE 802.3 standard. The MX98725 highly integrates with direct PCI bus interface, including PCI bus master with DMA channel capability, direct EEPROM as well as Boot ROM interface, and large on chip transmit/receive FIFOs. Also, the MX98725 is equipped with intelligent IEEE802.3u-compliant Nway auto-negotiation capability allowing a single RJ-45 connector to link with the other IEEE802.3u-compliant device without re-configuration. To optimize operating bandwidth, network data integrity and throughput, the proprietary Adaptive Network Throughput Control (ANTC) function is implemented. For detailed product specification information, please refer to the MX98725 data sheet.
3. HARDWARE DESIGN CONSIDERATIONS
3.1 SYSTEM APPLICATION BLOCK DIAGRAM A system block diagram for the MX98725 based Fast Ethernet adapter card is shown as following:
PCI Bus
Boot ROM
Osc 25MHz
MX98725
LED
EEPROM
Magnetic
RJ45
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MX98725
3.2 PCI CONNECTION The MX98725 provides direct PCI bus interface to PCI connector. Board designers should especially take care of the four pins of TDI, TDO, PRSNT1# & PRSNT2# that are only related to PCI bus connector. Boards that do not implement JTAG Boundary Scan should tight TDI and TDO together to prevent the scan chain from being broken. Both pins PRSNT1# and PRSNT2# should be connected to ground indicating that the board is physically presenting in a PCI slot and providing information about the total power requirements (less than 7.5W ) of the board. 3.3 OSCILLATOR The MX98725 is designed to operate with a 25MHz-oscillator module. The clock specification of this oscillator should meet 25MHz +/- 50PPM. Furthermore, if flash memory is used, one can change its contents via CSR9 and CSR10 (Refer to MX98725 data sheet). Detailed software programming example is described in section 4.6. 3.4 BOOT ROM The MX98725 supports a direct boot ROM interfaces allowing diskless workstations to remotely download operating system from network server. For proper operation, the access time of adapted EPROM should not excess 240ns. Furthermore, if flash memory is used, user could easily change its contents via CSR9 and CSR10. Detailed information of CSR9 and CSR10 please refer to MX98725 data sheet. In Section 4.6, an example of flash memory programming methods is listed. 3.5 SERIAL EEPROM The MX98725 provides pins EECS, BPA0 (EECK), BPA1 (EEDI) and BPD0 (EEDO) for directly accessing the serial EEPROM. BPA0-1 and BPD0 serve as SK (EECK), DI (EEDI) and DO (EEDO) respectively. The contents of the EEPROM include the ID information of the MX98725 (VendorID, DeviceID, Sub-vendorID, Sub-deviceID and MAC ID), and the configuration parameters for software driver. The EEPROM contents should be programmed according to MXIC' definition as mentioned in Appendix
CSR9 <28:31> LED0 0000 1111 Activity LED1 LED2 LED3 RX Goodlink TX
A. Detailed software programming example is described in section 4.5. 3.6 PROGRAMMABLE LED SUPPORT The MX98725 provides four pins LED0SEL, LED1SEL, LED2SEL and LED3SEL to control display LED. Displayed messages are programmable through setting CSR9 bit 28~31 to serve as Activity or Linkspeed, Goodlink or Link/ Activity, TX or Collision and RX or Full/Half Duplex LED respectively. The maximum sinking current of these output pins is 16mA. Current limiting resistor (560) should be added to ensure proper operation. The following indicates the configuration setting example table for LED display programming.
Linkspeed Link/Act
Collision F/H duplex
3.7 NETWORK INTERFACE TO MAGNETIC COMPONENT For isolating and impedance matching purpose, an isolating transformer with 1:1 transmit and 1:1 receive turns ratio is required for transmit and receive twisted pair interface. In Appendix B, several transformers that we had verified successfully with MX98725 are listed for quick reference purpose. 3.8 OPTIMIZED EQUALIZER COMPONENTS MXIC' Fast Ethernet solution utilizes adaptive equalizer to compensate the attenuation and phase distortion induced by different lengths of cable. To optimize transmit and receive signal quality, pins RTX and RTX2EQ should be connected to external resistors 560 (1%) and 1.4K (1%) and then to ground respectively. 3.9 Remote-Power-On and ACPI application MX98725 fully supports Remote-Power-On and ACPI that meets PC98 requirement for power-sensitive applications. To implement such advance features, two necessary conditions should be met at first: (1) After the AC power being plugged in, power supply must be continuously drained at least 400mA from auxiliary power, no matter the switch is in ON or OFF states. (2) Motherboard BIOS must support Remote-Power-On.
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MX98725
The auxiliary power and PCI bus power are decoupled via a power switch (FDC6324L). After the AC power core being plugged in, the MX98725 will automatically load network ID from EEPROM and begin to scan incoming packet. Once receiving magic packet from network, PMEB and EXTSTARTB of MX98725 will be asserted low and LANWAKE will be asserted high to wake up the host. PMEB will be asserted when one of the following conditions meet: (1) The MX98725 is in D1 state, PMCSR<8> and PMEB enable, and a magic packet is received. (2) The MX98725 is in D3-cold (power off) state, and a magic packet is received. PMEB can be disserted by: (1) Clearing PMCSR<8> (2) Writing 1 to PMCSR<15> (3) Turn on the host power
0xfffc); &physicaladdress); tx_resource[i]->buff_1_addr=physicaladdress; /* fill buffer_2_address tdes3 */ if (i==NumTXBuffers-1) j=0; else j=i+1; get_ea((void far *)(tx_resource[j], &physicaladdress); tx_resource[i]->buff_2_addr=physicaladdress; } } initializeTheReceiveRing() { unsigned int i,j; unsigned long physicaladdress; for (i=0; iframe_length=RDES0_OWN_BIT; rx_resource[i]->rstatus=0x0000; /* fill rdes1 */ rx_resource[i]->command=RDES1_BUFFRX_BUFFER_SIZE+rxpkt_size[i]; /* fill buffer_1_address rdes2 */ get_ea((void far *)(rx_resource[i]->rx_buffer_data), &physicaladdress); rx_resource[i]->buff_1_addr=physicaladdress; /* fill buffer_2_address rdes3 */ if (i==NumRXBuffers-1) j=0; else j=i+1; get_ea((void far *)(rx_resource[j], &physicaladdress); rx_resource[i]->buff_2_addr=physicaladdress; } } initialize() { unsigned long physicaladdress; NIC_read_reg(&csr6); NIC_write_reg(&csr6,csr6.value&(~(CSR6_SR|CSR6_ST))); delay(10); InitializeTheTransmitRing (6); InitializeTheReceiveRing (6); NIC_write_reg(&csr0,CSR0_L_SWR);
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4. DRIVER PROGRAMMING GUIDE
This chapter will provide you the necessary information for programming driver for the MX98725 based node. Initialization module is introduced first that describes how MX98725 is initialized before any other operations can commence, then followed by actual implementation examples for both transmit and receive operations. Programming differences between MX98713, MX98713A and MX98725 are also included that will help you to upgrade your own driver to support all MXIC' NIC product series. 4.1 INITIALIZATION
initializeTheTransmitRing() { unsigned int i,j; unsigned long physicaladdress; for (i=0; iownership=0x00; tx_resource[i]->tstatus=0x0000; tx_resource[i]->tdes0_unused=0x00; /* fill buffer_1_address tdes2 */ get_ea((void far *)(tx_resource[i]->tx_buffer_data),
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MX98725
delay(50); NIC_write_reg(&csr0,csr0shadow); get_ea((void far *)rx_resource[0],&physicaladdress); NIC_write_reg(&csr3,physicaladdress); get_ea((void far *)tx_resource[0],&physicaladdress); NIC_write_reg(&csr4,physicaladdress); NIC_read_reg(&csr16); NIC_write_reg(&csr7,csr7shadow); NIC_write_reg(&csr16,csr16shadow); //Clear status register NIC_write_reg(&csr5,(unsigned long)0xffffffff); NIC_write_reg(&csr6,csr6shadow); NIC_read_reg(&csr6); setup_frame(TDES1_SETUP_LAST,perfect); } NIC_read_reg(&csr6); NIC_write_reg(&csr6,csr6.value^CSR6_ST); break default: break; } } } } }
4.3 RECEPTION MODULE
bmrx() { unsigned char editmode,i,j; unsigned long physicaladdress; struct RX_RESOURCE *rcv_pointer; initialize(); rcv_pointer=rx_resource[0]; j=0; editmode=1; while (editmode) { // if data received if ((rcv_pointer->frame_length & 0x8000)==0) { j++; j%=6; if (rcv_pointer->rstatus & RDES0_LS) rx_error_detect(rcv_pointer->rstatus); rcv_pointer->frame_length |= 0x8000; rcv_pointer=rx_resource[j]; } if (kbhit()) { keycode_get(); if (M_code!=0) { switch (M_code) { case 0x1b: // ESC: quit editmode=0; break; default: break; } } } } }
4.2 TRANSMITION MODULE
bmtx() { unsigned char editmode, j; struct TX_RESOURCE *tx_pointer; initialize(); fill_pattern(6); //fill pattern NIC_write_reg(&csr6,csr6.value&(~CSR6_ST)); //stop NIC_read_reg(&csr6); NIC_write_reg(&csr6,csr6.value|CSR6_SF); //store and forware NIC_read_reg(&csr0) NIC_write_reg(&csr0,csr0.value|0x020000); //TAP=01 tx_pointer=tx_resource[0]; j=0; editmode=1; while (editmode) { if ((tx_pointer->ownership & 0x80)==0) { j++; j%=tx_pkt_num; if (tx_pointer->command & TDES1_LS_BIT) tx_error_detect(tx_pointer->tstatus); tx_pointer->ownership |= 0x80; tx_pointer=tx_resource[j]; } if (kbhit()) { keycode_get(); if (M_code!=0) { switch (M_code) { case 0x1b: // ESC: quit editmode=0; break; case 0x20:
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MX98725
4.4 CODING DIFFERENCE BETWEEN MX98713, MX98713A, MX98715 AND MX98725 4.4.1 SPEED SELECTION Speed selection of MX98713 are controlled by internal Nway registers. All the MII management commands should have the following structure:
4.5 EEPROM ACCESSING The following is a reference code for accessing the contents of EEPROM that stores ID information and node configuration for the MX98725.
/************************************* * Read all content from EEPROM **************************************/ eeprom_read() { unsigned int i, address, eeval; char bit; for (address=0; address<64; address++{ NIC_write_reg(&csr9,(unsigned long)0x04800); eeprom_serial_in(0); eeprom_serial_in(1); //command eeprom_serial_in(1); eeprom_serial_in(0); for(i=0; i<6; i++){ //address serial in bit = ((address>>(5-i)) & 0x01) ? 1:0; eeprom_serial_in(bit); } eeval=0; for(i=0; i<16; i++){ //dat serial out NIC_write_reg(&csr9,(unsigned long)0x04803); NIC_read_reg(&csr9); eeval += (((unsigned long)0x008 & csr9.value)>>3)<<(15i); NIC_write_reg(&csr9,(unsigned long)0x04801); } NIC_write_reg(&csr9,(unsigned long)0x04800); c46[address*2] = eeval & 0x0ff; c46[address*2+1] = (eeval >>8) & 0x0ff; } } /************************************* * Write a word to EEPROM **************************************/ eeprom_write(unsigned int address, unsigned int data) { unsigned int i; char bit; eeprom_wen(); NIC_write_reg(&csr9,(unsigned long)0x04800); eeprom_serial_in(0); eeprom_serial_in(1); //command eeprom_serial_in(0); eeprom_serial_in(1); for(i=0; i<6; i++){ //address serial in bit = ((address>>(5-i)) & 0x01) ? 1:0;
For detailed programming example, please refer to MX98713 application note. As for MX98713A, MX98715 and MX98725, Internal NWay registers are removed and protocol selection is controlled by Operation Mode Register (CSR6) and 10Base-T Control Register (CSR14)
NWay Active CSR6_PS CSR6_PCS CSR6_FD CSR14_ANE 100F 0 X 1 1 100H 1 1 1 0 10F 1 1 0 0 10H 0 X 1 0 0 X 0 0
4.4.2 ELSE REGISTERS SETTING FOR DEVELOPING YOUR OWN DRIVER There is an obvious change in setting the contents of CSR16 in comparison with MX98713. In MX98713, the offset 80h in IO space that is CSR16 must be set to "0x0f37XXXX" to bring this controller into normal operation mode before any initialization process can be started by driver. However, in MX98713A, MX98715 and MX98725, driver developers must set the CSR16 to be "0x0b3cXXXX" . In summary, the contents of CSR16 for MXIC 100Base NIC controllers should be set differently as follow: MX98713 = 0x0f37XXXX MX98713A = 0x0b3cXXXX MX98715 = 0x0b3cXXXX MX98725 = 0x0b3cXXXX Meanwhile, you could directly access the Nway auto-negotiation status from CSR20. Detailed format please refer to MX98725 data sheet.
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MX98725
eeprom_serial_in(bit); } for(i=0; i<16; i++){ //data serial in bit = ((data>>(15-i)) & 0x01) ? 1:0; eeprom_serial_in(bit); } NIC_write_reg(&csr9,(unsigned long)0x04800); NIC_write_reg(&csr9,(unsigned long)0x04801); i=0; do{ i++; NIC_read_reg(&csr9); } while ((!(csr9.value & 0x08)) && (i<10000)); NIC_write_reg(&csr9,(unsigned long)0x04800); if (i==10000) prstring ("Writing EEPROM error !!"); eeprom_wds(); } eeprom_wen() { NIC_write_reg(&csr9,(unsigned long)0x04800); eeprom_serial_in(0); eeprom_serial_in(1); eeprom_serial_in(0); eeprom_serial_in(0); eeprom_serial_in(1); eeprom_serial_in(1); eeprom_serial_in(0); eeprom_serial_in(0); eeprom_serial_in(0); eeprom_serial_in(0); NIC_write_reg(&csr9,(unsigned long)0x04800); } eeprom_wds() { NIC_write_reg(&csr9,(unsigned long)0x04800); eeprom_serial_in(0); eeprom_serial_in(1); eeprom_serial_in(0); eeprom_serial_in(0); eeprom_serial_in(0); eeprom_serial_in(0); eeprom_serial_in(0); eeprom_serial_in(0); eeprom_serial_in(0); eeprom_serial_in(0); NIC_write_reg(&csr9,(unsigned long)0x04800); } /************************************* * Serial inject a bit to EEPROM **************************************/
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eeprom_serial_in(unsigned int bit2) { NIC_write_reg(&csr9,(unsigned long)0x04800+4*bit2); NIC_write_reg(&csr9,(unsigned long)0x04803+4*bit2); NIC_write_reg(&csr9,(unsigned long)0x04801+4*bit2); }
4.6 Flash ROM accessing Following is an example code for accessing Macronix's flash ROM MX28F2000.
#define CYCLE1_ADDRESS (unsigned long)0x00005555 #define CYCLE2_ADDRESS (unsigned long)0x00002aaa FlashWrite (unsigned long FlashAddress, unsigned char FlashData) { NIC_write_reg(&csr10, FlashAddress); NIC_write_reg(&csr9, (unsigned long)(0x00003000 | FlashData)); } unsigned char FlashRead (unsigned long FlashAddress) { NIC_write_reg(&csr10, FlashAddress); NIC_write_reg(&csr9, (unsigned long)(0x00005000)); NIC_read_reg(&csr9); return ((unsigned char)(0xff & csr9.value)); } ResetToReadMode () { _disable(); FlashWrite (CYCLE1_ADDRESS, (unsigned char) 0xff); FlashWrite (CYCLE1_ADDRESS, (unsigned char) 0xff); _enable(); } unsigned char Read_ID_OK () { unsigned char manufactureID; unsigned char deviceID; ResetToReadMode (); _disable(); FlashWrite (CYCLE2_ADDRESS, (unsigned char) 0x90); manufactureID = FlashRead (CYCLE2_ADDRESS); FlashWrite (CYCLE2_ADDRESS, (unsigned char) 0x90); deviceID = FlashRead (CYCLE2_ADDRESS+1); _enable(); ResetToReadMode (); if ((manufactureID!=0xc2) | (deviceID!=0x2a)) return 0; else return 0xff; }
SetUpByteWriteCmd (unsigned long wraddr, unsigned char wrdata) { unsigned char tmp;
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MX98725
5. PCB LAYOUT RECOMMENDATIONS
The MX98725-based adapter board is strongly recommended to separate the power plane into 3 regions, i.e., digital, analog and receive region to isolate from digital noise and noise coupling between the transmitter and the receiver. These power pins in these three regions are shown in the table listed below. Each VDD pin also needs a 0.1uF capacitor located as close to the VDD pin as possible. Analog Region 3. VDD 4. GND 5. VDD 6. GND 7. VDD 8. GND 9. VDD 137. GND 138. VDD 140. GND 142. GND 144. VDD 143. GND 155. VDD 159. GND Receive Region 147. VDD 148. GND 145. VDD 146. GND 151. GND 152. VDD 153. GND 154. GND Digital Region Others
_disable(); FlashWrite (wraddr, (unsigned char) 0x40); FlashWrite (wraddr, wrdata); _enable(); tmp = FlashRead (wraddr); while (tmp != FlashRead(wraddr)) tmp=FlashRead(wraddr); ResetToReadMode (); } ChipErase () { unsigned char tmp; _disable(); FlashWrite (CYCLE1_ADDRESS, (unsigned char) 0x30); FlashWrite (CYCLE1_ADDRESS, (unsigned char) 0x30); _enable(); delay100us (); tmp = FlashRead (CYCLE1_ADDRESS); while (tmp != FlashRead(CYCLE1_ADDRESS)) tmp=FlashRead(CYCLE1_ADDRESS); ResetToReadMode (); } /*********************************************************/ main(argc,argv) /*********************************************************/ int argc; char *argv[]; { unsigned long i; // MX28F2000 manufactureID and DeviceID check if (!Read_ID_OK()) { printf("\nRead ID failed !!!\n"); exit(0); } // MX28F2000 erased ChipErase (); // MX28F2000 filled with all ` 0 ' for (i=0; i<=0x3ffff; i++) { SetUpByteWriteCmd (i, 0); ResetToReadMode (); } }
The power plane of designed PCB should be split into three regions. The below figure clearly describes an ideal power plane partition related to MX98725's pinout. To reduce noise incurred among power traces of these three regions, designers should allocate Ferrit Beads on the interface of +5V traces between digital and analog regions as well as between analog and receive regions. Such placement of Ferrit Beads implies that the power traces between digital and receive regions should be clearly isolated; all the power for receive region should be from analog region. All the traces and resistance/ capacitance components for these pins of MX98725 should be located in each specified regions. As for placement of the 25MHz oscillator, it is recommended to be apart from receive and analog regions as far as possible to prevent from the impact of harmonic noise.
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MX98725
Transformer RXRX+ TXTX+
Receive Region
Bead OSC 25MHz
155 154
145 144
137 135
Bead
9 10
Analog Region Digital Region MX98725
40 41
Fig. 2
The MX98725 should be placed as close to the transformer as possible to reduce the length of layout traces and potential noise from coupling on RXIP/N and TXOP/ N. The 100 resistor between RXIP and RXIN is suggested being located as close to the RXIP and RXIN pins of MX98725 as possible. The 49.9 pull up (VDD) resistors for TXOP and TXON pins should be placed as close to the TXOP and TXON pins of MX98725 as possible for impedance match purpose. The receive paths (traces of RXIP/N) need to be in parallel and have equal routing length on the component side of the PCB, and absolutely do not have any through hole on the receive paths to keep the signals clearance.
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MX98725
APPENDIX A: EEPROM FORMAT
BYTE OFFSET (HEX) 00-19 1a 1b 1c 1d 1e-39 3a 3b 3c-59 5a 5b 5c 5d 5e-6f 70 DESCRIPTIONS Reserved Magic Packet ID Byte1 Magic Packet ID Byte0 Magic Packet ID Byte3 Magic Packet ID Byte2 Reserved Magic Packet ID Byte5 Magic Packet ID Byte4 Reserved LSB of Sub-Device ID MSB of Sub-Device ID LSB of Sub-Vendor ID MSB of Sub-Vendor ID Reserved Network ID index: to indicate the starting address of Network ID in length of continuous 6 bytes. The content of this field could be in the range of 00-04h, or 10-14h, or 21-24h, or 31-34h Reserved, and should be set to 0 LED option: The content of this field will be read by driver for LED setting Bit0: CSR9 Bit 28, LED0SEL Bit1: CSR9 Bit 29, LED1SEL Bit2: CSR9 Bit 30, LED2SEL Bit3: CSR9 Bit 31, LED3SEL Reserved, and should be set to 0 LSB of Device ID MSB of Device ID LSB of Vendor ID MSB of Vendor ID Reserved, and should be set to 0
71-76 77
78-79 7a 7b 7c 7d 7e-7f
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MX98725
APPENDIX B: MAGNETIC COMPONENTS
1 BASIC ELECTRICAL SPECIFICATION Turn Ratio OCL LL Cww DCR Isolation Resistance Isolation Voltage Rise/Fall Time Insertion Loss (100 KHz to 100 MHz) CMDR & DCMR (100 KHz to 80 MHz) Cross Talk (100KHz to 80 MHz) 2 REFERENCE VENDORS Vendor Valor PE BelFuse Delta Taimic Transmit 1:1 Receive 1:1 350uH min measured between 0 and 70C with a 0.1V rms, 100KHz signal at a DC bias between 0 and 8mA. 0.4uH Max at >1MHz 18pF Max 0.9W Max per winding not less than 1GW @ 2000V rms 2000V rms Min @ 60Hz for 1 min 3ns Min 4ns Max -1.1 dB Max 38 dB Min -38 dB Max Part No ST6118 (PT4171S) PE68515 S558-5999-15 LF8200 HSIP-002
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MX98725
APPENDIX C: THE B.O.M. LIST OF MX98715 DEMO BOARD
ITEM 1 2 3 4 5 6 QUANTITY 2 1 4 4 1 24 REFERENCE C1, C25 C2 C3, C24, C37, C39 C4, C22, C36, C45 C5 C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C18, C20, C21, C27, C28, C29, C30, C32, C33, C41, C42, C46, C47 C19 C23 C26 C38, C40 D1, D2, D3, D4 J1, J2 L3 OSC1 Q1 R2 R3, R10, R11, R12 R4, R22, R23 R5 R9 R7 R8, R15, R18, R18, R20 R13, R14 R21, R24, R25 RJ1 U1 U2 U3 U4 PART 82p 470p 0.1u (0805) 22u 47p 0.1u (0603)
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
1 1 1 2 4 2 1 1 1 1 4 3 1 1 1 5 2 3 1 1 1 1 1
2.2u 0.01u/1KV (DIP) 820p 150p LED CON3 F.B. 25MHz (50PPM) Half size 2N3904 (SMD) 36 75 12K 100 0 1.4K 560 49.9 68K RJ-45 MX98725 MX28F2000P 93C46 ST6118 (VALOR), H1012 (Pulse), HSIP-002 (TAIMIC) PDC6324L
30
2
U5, U6
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MX98725
U6 1 R2 VO U T VO U T R 22 R 23 2 1 1 2K Q1 2N 3904 3 F D C 6 32 4 L 1 2K PVC C PVC C F D C 6 32 4 L VIN 4 VC C VO U T VIN LAN W AKE VC C S TB V C C 3 4 O N /O F F 5 VO U T O N /O F F 6 8K 2 5 6 8K R1 R2 R1 2 R 25 6 8K 3 6 R 24 1 6 R 21
U5 J1 S TB V C C LAN W AKE 1 2 3 C ON3
J2
S TB V C C
E XTS TA R T#
E XTS TA R T#
1 2 3
C ON3
FDC6324L:
F A I R C H I L D F D C 6 32 4 L I n te g ra t ed Lo a d S w itc h C on t a c t w ith N S 's a g en t . D at a s he e t: www. f a irc h ild s e m i.c o m TD I O C 46 0 .1 u PVC C B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 PC IC LK R EQ # PVC C AD 31 AD 29 AD 27 AD 25 C /B E 3 # C /B E 3 # AD 23 AD 21 AD 19 AD 17 C /B E 2 # IR D Y # D E V S E L# PER R # SER R # C /B E 1 # AD 14 AD 12 AD 10 -12 V TC K GN D TD O VD D VD D I N TB # I N TD # P R S N T1# R ESER VE P R S N T2# GN D GN D R ESER VE GN D C LK GN D R EQ # V D D (I / O ) AD 31 AD 29 GN D AD 27 AD 25 +3. 3 V C /B E 3 # AD 23 GN D AD 21 AD 19 +3. 3 V AD 17 C /B E 2 # GN D IR D Y # +3. 3 V D E V S E L# GN D LOC K # PER R # +3. 3 V SER R # +3. 3 V C /B E 1 # AD 14 GN D AD 12 AD 10 GN D AD 8 AD 7 AD 5 AD 3 AD 1 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 VC C C 47 AD 8 AD 7 +3. 3 V AD 5 AD 3 GN D AD 1 V D D (I / O ) AC K64# VD D VD D TR S T# +1 2 V TM S TD I VD D IN TA # IN TC # VD D R ESER VE V D D (I / O ) R ESER VE GN D GN D R ESER VE R S T# V D D (I / O ) G N T# GN D PME# A D 30 +3. 3 V A D 28 A D 26 GN D A D 24 ID S E L +3. 3 V A D 22 A D 20 GN D A D 18 A D 16 +3. 3 V F R A ME # GN D TR D Y # GN D S TO P # +3. 3 V SD ON E SBO # GN D PAR A D 15 +3. 3 V A D 13 A D 11 GN D AD 9 C /BE0# +3. 3 V AD 6 AD 4 GN D AD 2 AD 0 V D D (I / O ) R E Q 6 4# VD D VD D
P1
1 2V
PC IC LK
APPENDIX D: MX98725 APPLICATION SCHEMATIC CIRCUITS
R EQ #
C /B E 2 # IR D Y # D E V S E L# PER R # SER R # C /B E 1 #
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62
+ TD I O I N TA # PVC C PVC C
C 45 2 2u
I N TA #
R S T# G N T# PME# AD 30 AD 28 AD 26 AD 24 ID SEL AD 22 AD 20 AD 18 AD 16 F R AME# TR D Y # S TO P # PVC C
R S T#
G N T#
PME#
ID SEL
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Title S ize B D at e :
F R AME#
TR D Y #
S TO P #
PAR AD 15 AD 13 AD 11 AD 9 C /B E 0 # AD 6 AD 4 AD 2 AD 0
PAR
C /B E 0 #
D.1 PCI BUS INTERFACE
0 .1 u
P C I 5V _A A D [ 0. . 31 ] A D [ 0. . 31 ]
NOTE:
G E R B E R F I LE S L I S TA R T01 . P H O A R T04 . P H O S S T0 1 26 . P H O D D 04 2 4. P H O S M 0 12 8 .P H O S M 0 42 9 .P H O P G P 0 2 25 . P H O -- G N D L A Y E R 2 \ P G P 0 3 25 . P H O -- V C C LA Y E R 3 /
FOR 2-LAYER PCB ADD THESE 2 FILES FOR 4-LAYER PCB
M A C R O N I X I N TE R N A TI O N A L C O . , L TD
P C I B us an d A C P I c irc u it
D oc u m e n t N um be r M X9 8 7 25 D E MO B O A R D
R ev C
F rid ay , M ay 2 2 , 1 99 8
S h e et
2
of
3
P/N:PM0525
12
INDEX
MX98725
DEVSEL# T RDY# I RDY# FRAME# IDSEL C/BE0# C/BE1# C/BE2# C/BE3# VCC AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 C36 22u C32 0.1u 37 53 65 80 38 54 57 58 59 60 62 63 64 15 16 17 18 19 14 20 21 23 24 27 32 33 36 41 42 44 45 48 49 51 52 66 69 70 73 74 75 78 79 82 83 86 87 90 91 93 94 C41 C42 VCC 25 26 28 29 46 47 61 71 72 88 89 95 96 126 127 137 140 144 155 3 6 8 147 148 151 152 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDDA VDDA VDDA VDDA VDDA VDDA VDDA VDDR VDDR VDDR VDDR 0.1u C33 0.1u C30 0.1u C15 0.1u C29 0.1u C/BE3# C/BE2# C/BE1# C/BE0# IDSEL FRAME# I RDY# T RDY# DEVSEL# STOP# PERR# SERR# PAR INT # RST # PCICLK GNT # REQ# PME# AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 0.1u + AD[0..31] PME# REQ# GNT # PCICLK RST # I NT A# PAR SERR# PERR# STOP# DEVSEL# T RDY# I RDY# FRAME# IDSEL C/BE0# C/BE1# C/BE2# C/BE3# AD[0..31]
STOP# PERR# SERR# PAR I NT A# RST # PCICLK GNT # REQ# PME#
VCC D1 LED0 2 LED D2 LED1 2 LED D3 LED2 2 LED D4 LED3 2 1 1 1 1 R18 560 R15 560 R19 560 R20
U1 LED
560
U2 BPA0(EECK) BPA1(EEDI) BPA2 BPA3 BPA4 BPA5 BPA6 BPA7 BPA8 BPA9 BPA10 BPA11 BPA12 BPA13 BPA14 BPA15 BPA16 BPA17 110 111 112 113 114 115 116 117 118 122 123 124 125 130 131 132 108 107 FCS# FOE# FWE# BPD7 BPD6 BPD5 BPD4 BPD3 BPD2 BPD1 BPD0(EEDO) EECS 120 121 119 99 100 101 102 103 104 105 106 109 133 LED0 134 LED1 135 LED2 136 LED3 LANW AKE EXTST ART # EN_RPO 11 12 13 BPA0 BPA1 BPA2 BPA3 BPA4 BPA5 BPA6 BPA7 BPA8 BPA9 BPA10 BPA11 BPA12 BPA13 BPA14 BPA15 BPA16 BPA17 FCS# FOE# FWE# BPD7 BPD6 BPD5 BPD4 BPD3 BPD2 BPD1 BPD0 EECS LED0 LED1 LED2 LED3 LANW AKE EXTST ART # U3 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 30 R9 0 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 MX28F2000P DIP Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 CE OE W E VPP VCC GND 13 14 15 17 18 19 20 21 22 24 31 1 VCC 32 C7 16 0.1u C6 0.1u BPD0 BPD1 BPD2 BPD3 BPD4 BPD5 BPD6 BPD7 FCS# FOE# FWE#
U2 Type
FLASH: 32 pins DIP Programming with 12V EPROM: 28 pins DIP on pin3-30 position
VCC L3 C28 0.1u VDDR 22u F.B. VDDA C22 + VDDA
VDDA
12V
MX98725
A A
C17 0.1u R6 0 VCC
VDDA C18 0.1u C14 0.1u C13 0.1u C20 0.1u C10 0.1u GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
D.2 MX98725 AND FRONT-END CIRCUITS
22 30 31 34 35 39 40 43 50 55 56 67 68 76 77 81 84
B NOTE:
Select A for FLASH use. Select B for EPROM use.
LANW AKE EXTST ART # VCC RT X 2EQ 10 EECS BPA0 BPA1 BPD0 1 2 3 4 CS SK DI DO VCC NC NC GND 8 7 6 5 C27 VCC EECS BPA0 1 2 3 4
REV. 1.1, JUL. 10, 1998
0.1u 93C46 DIP U4 15 T D+ T X+ 11 14 T D10+ CT 12 16 T DTX10 1 RD+ RX + 7 3 CT CT 5 2 RDRX6 ST 6118(VALOR) H1012(Pulse) HSIP-002(TAIMIC) R3 75 R12 75 R10 75 C23 0.01u/1KV(DIP) MACRONI XI NT ERNAT IONAL CO., LT D. T itle MX98725 CIRCUIT Siz e B Date: Document Number MX98725 DEMO BOARD Monday, May 25, 1998
U3X
NC VCC CS SK GND GND GND GND GND GND GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDR GNDR GNDR GNDR CKREF TXON EQT EST TXOP RT X RX IN RDA RX IP CPK 85 92 97 98 128 129 138 142 143 158 159 4 5 7 9 145 146 153 154 1 2
NC GND DO DI
8 7 6 5
BPD0 BPA1
93C46X SMD MX98725 141 139 149 160 150 156 157 R13
L1 VDDA F.B. C9 0.1u VCC 22u VDDR C4 + VDDR
RJ45 USE ALL-SHIELDED-COVER JACK. VDDA OSC25M RDA RT X 2EQ RT X TXOP L2 F.B. OSC1 OSC 14 C19 + C16 VCC 25MHz(50PPM) Half siz e GND 8 7 49. 9 C21 R2 36 C5 47p R1 300 2.2u 0.1u R4 12K R7 1.4K R8 560 RX IN TXON VDDA RX IP R14 49. 9 R5 100 C8 0.1u
RJ1
VDDR 0.1u C11 0.1u
C12
1 2 3 4 5 6 7 8
TXO+ T XORX I+ NC NC RX I NC NC
RJ-45
R11 75 0.1u VCC C39 L3 Ferrit Bead(F.B.) MAG.LAYERS SCIENT IFI C-TECHNICS CO.,LTD P/N: MLB-321611-2000A-N2 www.maglayers.com.tw TEL: 886-3-5517388 0.1u(0805) C40 150p C37 0.1u(0805) C24 0.1u(0805) C26 820p C25 82p 0.1u(0805) C38 150p
NOTE: L1, L2 are shorted on PCB.
C3
C2 470p
C1 82p
Rev C
Sheet
3
of
3
P/N:PM0525
FOR EMI & CE TEST.
13
INDEX
MX98725
REVISION HISTORY
Revision No. 1.1 Description To modify resistor R7 value from 1.5K 1.4K P.2, P.11, P.13) Date 07/10/1998
P/N:PM0525
REV. 1.1, JUL. 10, 1998
14
INDEX
MX98725
MACRONIX INTERNATIONAL CO., LTD.
HEADQUARTERS:
TEL:+886-3-578-8888 FAX:+886-3-578-8887
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TEL:+32-2-456-8020 FAX:+32-2-456-8021
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MACRONIX AMERICA, INC.
TEL:+1-408-453-8088 FAX:+1-408-453-8488
CHICAGO OFFICE:
TEL:+1-847-963-1900 FAX:+1-847-963-1909
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the rignt to change product and specifications without notice.
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